set_property PACKAGE_PIN U8 [get_ports {CLK_IN_D_0_clk_p[0]}]
set_property PACKAGE_PIN L4 [get_ports {pcie_mgt_0_txp[0]}]
set_property PACKAGE_PIN M2 [get_ports {pcie_mgt_0_txp[1]}]
set_property PACKAGE_PIN N4 [get_ports {pcie_mgt_0_txp[2]}]
set_property PACKAGE_PIN P2 [get_ports {pcie_mgt_0_txp[3]}]
set_property PACKAGE_PIN T2 [get_ports {pcie_mgt_0_txp[4]}]
set_property PACKAGE_PIN U4 [get_ports {pcie_mgt_0_txp[5]}]
set_property PACKAGE_PIN V2 [get_ports {pcie_mgt_0_txp[6]}]
set_property PACKAGE_PIN Y2 [get_ports {pcie_mgt_0_txp[7]}]
set_property PACKAGE_PIN V22 [get_ports sys_rst_n_0]
set_property IOSTANDARD LVCMOS33 [get_ports sys_rst_n_0]
set_property PULLUP true [get_ports sys_rst_n_0]
set_property PACKAGE_PIN R24 [get_ports user_lnk_up_0]
set_property IOSTANDARD LVCMOS33 [get_ports user_lnk_up_0]


#############SPI Configurate Setting##################
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]

set_property PACKAGE_PIN D27 [get_ports clk_in1_50M]
set_property IOSTANDARD LVCMOS18 [get_ports clk_in1_50M]
set_property PACKAGE_PIN T20 [get_ports DDR_init_calib_complete_0]
set_property IOSTANDARD LVCMOS33 [get_ports DDR_init_calib_complete_0]
